Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh, et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. A three-dimensional NAND memory structure includes an alternating stack of insulating layers and electrically conductive layers. A high device density is preferred in order to provide cost-effective manufacturing of such three-dimensional NAND memory structures.